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<title>DEC—Decrement by 1 </title></head>
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<h1>DEC—Decrement by 1</h1>
<table>
<tr>
<th>Opcode</th>
<th>Instruction</th>
<th>Op/En</th>
<th>64-Bit Mode</th>
<th>Compat/Leg Mode</th>
<th>Description</th></tr>
<tr>
<td>FE /1</td>
<td>DEC <em>r/m8</em></td>
<td>M</td>
<td>Valid</td>
<td>Valid</td>
<td>Decrement <em>r/m8</em> by 1.</td></tr>
<tr>
<td>REX + FE /1</td>
<td>DEC <em>r/m8</em><sup>*</sup></td>
<td>M</td>
<td>Valid</td>
<td>N.E.</td>
<td>Decrement <em>r/m8</em> by 1.</td></tr>
<tr>
<td>FF /1</td>
<td>DEC <em>r/m16</em></td>
<td>M</td>
<td>Valid</td>
<td>Valid</td>
<td>Decrement <em>r/m16</em> by 1.</td></tr>
<tr>
<td>FF /1</td>
<td>DEC <em>r/m32</em></td>
<td>M</td>
<td>Valid</td>
<td>Valid</td>
<td>Decrement <em>r/m32</em> by 1.</td></tr>
<tr>
<td>REX.W + FF /1</td>
<td>DEC <em>r/m64</em></td>
<td>M</td>
<td>Valid</td>
<td>N.E.</td>
<td>Decrement <em>r/m64</em> by 1.</td></tr>
<tr>
<td>48+rw</td>
<td>DEC <em>r16</em></td>
<td>O</td>
<td>N.E.</td>
<td>Valid</td>
<td>Decrement <em>r16</em> by 1.</td></tr>
<tr>
<td>48+rd</td>
<td>DEC <em>r32</em></td>
<td>O</td>
<td>N.E.</td>
<td>Valid</td>
<td>Decrement <em>r32</em> by 1.</td></tr></table>
<p><strong>NOTES:</strong></p>
<p>*</p>
<p>In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.</p>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>M</td>
<td>ModRM:r/m (r, w)</td>
<td>NA</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>O</td>
<td>opcode + rd (r, w)</td>
<td>NA</td>
<td>NA</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Subtracts 1 from the destination operand, while preserving the state of the CF flag. The destination operand can be a register or a memory location. This instruction allows a loop counter to be updated without disturbing the CF flag. (To perform a decrement operation that updates the CF flag, use a SUB instruction with an immediate operand of 1.)</p>
<p>This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.</p>
<p>In 64-bit mode, DEC r16 and DEC r32 are not encodable (because opcodes 48H through 4FH are REX prefixes). Otherwise, the instruction’s 64-bit mode default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits.</p>
<p>See the summary chart at the beginning of this section for encoding data and limits.</p>
<h2>Operation</h2>
<pre>DEST ← DEST – 1;</pre>
<h2>Flags Affected</h2>
<p>The CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to the result.</p>
<h2>Protected Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#GP(0)</td>
<td>
<p>If the destination operand is located in a non-writable segment.</p>
<p>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</p>
<p>If the DS, ES, FS, or GS register contains a NULL segment selector.</p></td></tr>
<tr>
<td>#SS(0)</td>
<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr>
<td>#PF(fault-code)</td>
<td>If a page fault occurs.</td></tr>
<tr>
<td>#AC(0)</td>
<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr>
<tr>
<td>#UD</td>
<td>If the LOCK prefix is used but the destination is not a memory operand.</td></tr></table>
<h2>Real-Address Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#GP</td>
<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr>
<td>#SS</td>
<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr>
<td>#UD</td>
<td>If the LOCK prefix is used but the destination is not a memory operand.</td></tr></table>
<h2>Virtual-8086 Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#GP(0)</td>
<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr>
<td>#SS(0)</td>
<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr>
<td>#PF(fault-code)</td>
<td>If a page fault occurs.</td></tr>
<tr>
<td>#AC(0)</td>
<td>If alignment checking is enabled and an unaligned memory reference is made.</td></tr>
<tr>
<td>#UD</td>
<td>If the LOCK prefix is used but the destination is not a memory operand.</td></tr></table>
<h2>Compatibility Mode Exceptions</h2>
<p>Same exceptions as in protected mode.</p>
<h2>64-Bit Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#SS(0)</td>
<td>If a memory address referencing the SS segment is in a non-canonical form.</td></tr>
<tr>
<td>#GP(0)</td>
<td>If the memory address is in a non-canonical form.</td></tr>
<tr>
<td>#PF(fault-code)</td>
<td>If a page fault occurs.</td></tr>
<tr>
<td>#AC(0)</td>
<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr>
<tr>
<td>#UD</td>
<td>If the LOCK prefix is used but the destination is not a memory operand.</td></tr></table></body></html>